module wb_ack(
	input	CLK_I,
	input	RST_I,
	input	CYC_I,
	input	STB_I,
	output	ACK_O
);

reg	ack;

assign	ACK_O = ack;

always @(posedge CLK_I) begin
	if (RST_I) begin
		ack <= 1'b0;
	end else begin
		ack <= CYC_I & STB_I & ~ack;
	end
end

endmodule
